/****************************************************************************** 
 * LPC24xx Standard Peripheral Library
 * Version:  1.0.0
 * 
 *  Copyright (C) 2012  Timothy Gack
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301  USA 
 *******************************************************************************
 * General Purpose Input/Output (GPIO)
 *
 * Port0 - Fast/Legacy selectable, Interrupt enabled
 * Port1 - Fast/Legacy selectable
 * Port2 - Fast only, Interrupt enabled
 * Port3 - Fast only
 * Port4 - Fast only
 *
 *******************************************************************************/
#ifndef _LPC24XX_GPIO_H_
#define _LPC24XX_GPIO_H_


#include "lpc24xx_std_includes.h"

#ifdef __cplusplus
extern "C" {
#endif

typedef enum _PIN_DIRECTION_
{
  DDR_IN = 0,
  DDR_OUT = 1
}PIN_DIRECTION;


/*
 * GPIO Register Types
 */
typedef union _IOPIN_TYPE_
{
  uint32_t value;
  struct _IOPIN_TYPE_BITFIELDS_
  {
    unsigned b0 : 1;
    unsigned b1 : 1;
    unsigned b2 : 1;
    unsigned b3 : 1;
    unsigned b4 : 1;
    unsigned b5 : 1;
    unsigned b6 : 1;
    unsigned b7 : 1;
    unsigned b8 : 1;
    unsigned b9 : 1;
    unsigned b10 : 1;
    unsigned b11 : 1;
    unsigned b12 : 1;
    unsigned b13 : 1;
    unsigned b14 : 1;
    unsigned b15 : 1;
    unsigned b16 : 1;
    unsigned b17 : 1;
    unsigned b18 : 1;
    unsigned b19 : 1;
    unsigned b20 : 1;
    unsigned b21 : 1;
    unsigned b22 : 1;
    unsigned b23 : 1;
    unsigned b24 : 1;
    unsigned b25 : 1;
    unsigned b26 : 1;
    unsigned b27 : 1;
    unsigned b28 : 1;
    unsigned b29 : 1;
    unsigned b30 : 1;
    unsigned b31 : 1;
  }bits;
}IOPIN_TYPE, *LP_IOPIN_TYPE;



/* GPIO overall Interrupt status register */
typedef union _IO_INT_STAT_TYPE_
{
  uint32_t value;
  struct _IO_OVERALL_INT_STAT_TYPE_BITFIELDS_
  {
      unsigned p0Int : 1;
      unsigned reserved0 : 1;
      unsigned p2Int : 1;
      unsigned reserved1 : 29;
  }bits;
}IO_INT_STAT_TYPE, *LP_IO_INT_STAT_TYPE;

/* GPIO Interrupt Enable for Rising edge register */
typedef union _IO_INT_TYPE_
{
  uint32_t value;
  struct _IO_INT_TYPE_BITFILEDS_
  {
    unsigned b0 : 1;
    unsigned b1 : 1;
    unsigned b2 : 1;
    unsigned b3 : 1;
    unsigned b4 : 1;
    unsigned b5 : 1;
    unsigned b6 : 1;
    unsigned b7 : 1;
    unsigned b8 : 1;
    unsigned b9 : 1;
    unsigned b10 : 1;
    unsigned b11 : 1;
    unsigned b12 : 1;
    unsigned b13 : 1;
    unsigned b14 : 1;
    unsigned b15 : 1;
    unsigned b16 : 1;
    unsigned b17 : 1;
    unsigned b18 : 1;
    unsigned b19 : 1;
    unsigned b21 : 1;
    unsigned b22 : 1;
    unsigned b23 : 1;
    unsigned b24 : 1;
    unsigned b25 : 1;
    unsigned b26 : 1;
    unsigned b27 : 1;
    unsigned b28 : 1;
    unsigned b29 : 1;
    unsigned b30 : 1;
    unsigned b31 : 1;
  }bits;
}IO_INT_TYPE, *LP_IO_INT_TYPE;


/* GPIO Register Definitions */
#define IOPIN0 (*(volatile IOPIN_TYPE *)(GPIO_BASE_ADDR + 0x00))
#define IOSET0 (*(volatile IOPIN_TYPE *)(GPIO_BASE_ADDR + 0x04))
#define IODIR0 (*(volatile IOPIN_TYPE *)(GPIO_BASE_ADDR + 0x08))
#define IOCLR0 (*(volatile IOPIN_TYPE *)(GPIO_BASE_ADDR + 0x0C))
#define IOPIN1 (*(volatile IOPIN_TYPE *)(GPIO_BASE_ADDR + 0x10))
#define IOSET1 (*(volatile IOPIN_TYPE *)(GPIO_BASE_ADDR + 0x14))
#define IODIR1 (*(volatile IOPIN_TYPE *)(GPIO_BASE_ADDR + 0x18))
#define IOCLR1 (*(volatile IOPIN_TYPE *)(GPIO_BASE_ADDR + 0x1C))

#define IO0_INT_EN_R (*(volatile IO_INT_TYPE *)(GPIO_BASE_ADDR + 0x90))
#define IO0_INT_EN_F (*(volatile IO_INT_TYPE *)(GPIO_BASE_ADDR + 0x94))
#define IO0_INT_STAT_R (*(volatile IO_INT_TYPE *)(GPIO_BASE_ADDR + 0x84))
#define IO0_INT_STAT_F (*(volatile IO_INT_TYPE *)(GPIO_BASE_ADDR + 0x88))
#define IO0_INT_CLR (*(volatile IO_INT_TYPE *)(GPIO_BASE_ADDR + 0x8C))

#define IO2_INT_EN_R (*(volatile IO_INT_TYPE *)(GPIO_BASE_ADDR + 0x90))
#define IO2_INT_EN_F (*(volatile IO_INT_TYPE *)(GPIO_BASE_ADDR + 0x94))
#define IO2_INT_STAT_R (*(volatile IO_INT_TYPE *)(GPIO_BASE_ADDR + 0x84))
#define IO2_INT_STAT_F (*(volatile IO_INT_TYPE *)(GPIO_BASE_ADDR + 0x88))
#define IO2_INT_CLR (*(volatile IO_INT_TYPE *)(GPIO_BASE_ADDR + 0x8C))

#define IO2_INT_STAT (*(volatile IO_INT_STAT_TYPE *)(GPIO_BASE_ADDR + 0x80))


/* Fast I/O setup */
#define FIO0DIR   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x00))
#define FIO0MASK  (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x10))
#define FIO0PIN   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x14))
#define FIO0SET   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x18))
#define FIO0CLR   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x1C))

#define FIO1DIR   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x20))
#define FIO1MASK  (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x30))
#define FIO1PIN   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x34))
#define FIO1SET   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x38))
#define FIO1CLR   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x3C))

#define FIO2DIR   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x40))
#define FIO2MASK  (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x50))
#define FIO2PIN   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x54))
#define FIO2SET   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x58))
#define FIO2CLR   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x5C))

#define FIO3DIR   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x60))
#define FIO3MASK  (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x70))
#define FIO3PIN   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x74))
#define FIO3SET   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x78))
#define FIO3CLR   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x7C))

#define FIO4DIR   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x80))
#define FIO4MASK  (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x90))
#define FIO4PIN   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x94))
#define FIO4SET   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x98))
#define FIO4CLR   (*(volatile IOPIN_TYPE *)(FIO_BASE_ADDR + 0x9C))

/* TODO: Create structures for WORD, HALF-WORD, and BYTE access */



#ifdef __cplusplus
}
#endif

#endif
